On-chip decoupling capacitors (commonly referred to as “decaps”) are typically used to prevent noise-related circuit degradation. More specifically, in advanced electronic computing systems, the decoupling capacitors serve as a charge reservoir to support instantaneous current surges that accompany simultaneous circuit switching. Decoupling capacitors may be employed on chip and across all levels of packaging, including single chip and multi chip modules, board and back plane. In addition, these passive components may be utilized in the power distribution systems for integrated circuits (IC) to reduce the simultaneous circuit switching noise.
Conventional decoupling capacitors are formed either as planar capacitors or trench type capacitors. In trench type capacitors, a trench is made directly in the silicon wafer and the sidewalls of the trench are used for the capacitor dielectric. For example, a deep hole is etched out of a Si-containing substrate wafer by a commonly used dry etch method known as reactive ion etching (RIE). A dielectric material usually with a high dielectric constant is deposited in a form of a conformal layer inside the hole. The inner surface on one side of the trench, and a conductive or a semiconductor material fill on the other side of the dielectric material serve as capacitor plates. The film thickness of the dielectric material is inversely proportional to the charge the film can hold. Thus, the thickness of the film is typically kept to a minimum to the extent allowed by the process capability. The surface area of the dielectric film is directly proportional to the charge holding capacity, also known as capacitance.
In this manner, the planar area of trench capacitors (e.g., the “footprint” on the top surface of the wafer) can be made fairly small. Moreover, as the trenches are processed prior to the polygate conductor module, there is no issue of trench capacitors causing across chip linewidth variation (ACLV) problems. However, a significant detractor of using a trench capacitor approach as a decoupling capacitors is the process complexity and cost. Moreover, the depth of deep trench capacitors is often limited by RIE lag.
RIE lag is a phenomenon that limits etching depth as a function of the critical dimension (e.g., width or diameter when viewed in plan view) of the printed image on the surface of a wafer being etched. RIE lag is an artifact of the long diffusion path from the surface of the wafer to bottom of the trench. The long diffusion path limits the availability of reactive etch species at the etch front (e.g., leading edge), and also limits the ability to evacuate the reaction by-products. RIE lag is particularly prevalent when etching high aspect ratio trench holes, where aspect ratio is defined as the ratio of the depth of the etched structure relative to its width or its diameter in plan view (e.g., the critical dimension).
Trench-type decoupling capacitors may be used in chips being prepared for three-dimensional integration (e.g., stack packages, etc.). Such chips typically include at least one through silicon via (TSV) that provides an electrical connection between chips that are vertically stacked, one atop another. However, fabricating a deep trench capacitor and a TSV in a chip can be prohibitively expensive in terms of process complexity and cost.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.